400G QSFP112 DR4 Optical Transceiver
LAQ70-DR4
Product Description
Link-all's LAQ70-DR4 is 400GBASE-DR4 / 2x200G-DR2 / 4x100GBASE-DR optical transceivers that support
aggregate bit rates of 425 Gbps over parallel single mode fiber media (PSM). The host electrical interface has 4
lanes operating with PAM4 signaling at 53.125 GBaud. The same signaling is used in the optical interface, which
consists of 4 duplex pairs of single mode fibers (SMFs) that transmit and receive a single wavelength over 2 m ~
500 m. Superior Tx performance and reliability is achieved through Link-all's advanced integrated design using
SiP engine (PIC with Quad MZM and SMT Quad DRV) and 2 Uncooled CW DFB Lasers with Non-hermetic COB.
As the optical connector, MPO-12 is applied.
Product Features
400GAggregation Mode: 400GBASE-DR4 / 400GAUI-4-S/L
200G Breakout Mode: 2x 200G-DR2 / 2x 200GAUI-2-S/L
100G Breakout Mode: 4x 100GBASE-DR / 4x 100GAUI-1-S/L
QSFP112 MSA compliant
MPO-12 connector with 8° angled end-face
Power consumption <9.5 W
Operating case temperature: 0 to 70 ºC
CMIS 5.1 management interface
Applications
Data Center 400GE 500 m SMF links
400GE to 4x 100GE breakout over 500 m
Description:400G QSFP112 1311nm-500M(FEC)-MTP/MPO-12, Commercial Temperature
Notes:
If you need more customized services, please contact us.
Function Descriptions
Link-all ' s LAQ70-DR4 is a 400G optical transceiver compliant to the QSFP112 form factor that supports
400GBASE-DR4 optical interface (IEEE Std 802.3-2022 Section 8) or two independent bundle of 2x 200G-DR
optical interfaces or four independent 100GBASE-DR optical interfaces (IEEE Std 802.3- 2022 Section 8). The
signaling per lane on both the optical and electrical interfaces is 53.125 GBaud PAM4 (106.25 Gbps/lane) for an
aggregate bit rate of 425 Gbps. The electrical interface complies to 400GAUI-4 or 2x 200GAUI-2 or 4x 100GAUI-1
(IEEE Std 802.3ck-2022). For error-free transmission, the host must provide KP4 FEC encoding, as specified in
IEEE Std 802.3-2018 Section 8 . By selecting the application code, the individual lanes of the module can be
configured to operate in 400 GbE mode or 2x 200 GbE mode or 4x 100 GbE mode. 400 GbE mode applies to
lanes 0-3 and groups them so that they operate as single 400 G data paths. 2x 200 GbE mode applies 200 GbE
to each of lanes 0-1 and 2-3 and groups them so that they operate as two independent 200 G data paths. 4x 100
GbE mode applies 100 GbE across all lanes, and allows each lane to operate as an independent 100 G data path.
The functional block diagram for the module is shown in Figure below. The arrangement of fibers for each
connector type is specified in the QSFP112 MSA Specification. The management interface complies to CMIS 5.1.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings will
cause permanent damage and/or adversely affect device reliability
Operating Environments
Electrical and optical characteristics below are defined under this operating environment, unless otherwise
specified.
Electrical Characteristics
Note:
1. Electrical module output is squelched for loss of optical input signal.
2. IEEE Std 802.3ck-2022
Optical Characteristics(Per lane)
Note:
1. Average launch power, each lane (min) is informative and not the principal indicator of signal strength.A
transmitter with launch power below this value cannot be compliant; however, a value above this does not ensure
compliance.
2. Even if the TDECQ < 1.4 dB, the OMAouter (min) must exceed these values.
3. Ceq is a coefficient defined in IEEE Std 802.3-2022 section 8 [1] clause 121.8.5.3 which accounts for reference
equalizer noise enhancement.
4. Transmitter reflectance is defined looking into the transmitter.
5. Average receive power, each lane (min) is informative and not the principal indicator of signal strength.A
received power below this value cannot be compliant; however, a value above this does not ensure compliance.
6. For when Pre-FEC BER is 2.4 x 10-4.
7. Defined for an input signal with SECQ between 0.9dB and 3.4dB. An ideal TX has a SECQ equal to
0.9dB. Link power budget includes 0.1dB MPI (Multi-Path Interference) penalty.
8. Measured with conformance test signal at TP3 (see IEEE Std 802.3-2022 section 8 [1] clause
124.8.9) for the BER specified in IEEE Std 802.3-2022 section 8 [1] 124.1.1.
9. Link power budget includes 0.1dB MPI penalty.
10. These test conditions are for measuring stressed receiver sensitivity. They are not characteristics of the
receiver.
RX_LOS Characteristics
High Speed Data Interface
Rx(n)(p/n)
Rx(n)(p/n) are QSFP112 module receiver data outputs. Rx(n)(p/n) are AC-coupled 100 ohm differential lines that
should be terminated with 100 ohm differentially at the Host ASIC(SerDes). The AC coupling is inside the
QSFP112 module and not required on the Host board. When properly terminated, the differential voltage swing is
less than or equal to 900 mVpp or as defined by the relevant standard, or whichever is less.
Output squelch for loss of optical input signal, hereafter Rx Squelch, is required and functions as follows. In the
event of the Rx input signal on any optical port becoming equal to or less than the level required to assert LOS or
in the event of an Rx CDR LOL being asserted, then the receiver output(s) associated with that Rx port is
squelched and the associated Rx LOS / Rx CDR LOL flags set. A single Rx optical port can be associated with
more than one Rx output. In the squelched state output impedance levels are maintained while the differential
voltage amplitude is less than 50 mVpp.
Tx(n)(p/n)
Tx(n)(p/n) are QSFP112 module transmitter data inputs. They are AC-coupled 100 ohm differential lines with 100
Ohm differential terminations inside the QSFP112 optical module. The AC coupling is implemented inside the
QSFP112 optical module and not required on the Host board.
Output squelch for loss of electrical signal, hereafter Tx Squelch, is functioned. Where implemented it functions as
follows. In the event of the differential, peak-to-peak electrical signal amplitude on any electrical input lane
becoming less than 70 mVpp, or in the event of a Tx CDR LOL being asserted, then the transmitter optical output
associated with that electrical input lane is squelched and the associated Tx LOS / Tx CDR LOL flags set. If
multiple electrical input lanes are associated with the same optical output lane, the loss of any of the incoming
electrical input lanes causes the optical output lane to be squelched.
For applications, e.g., Ethernet, where the transmitter off condition is defined in terms of average power,
squelching by disabling the transmitter is recommended and for applications, e.g., InfiniBand, where the
transmitter off condition is defined in terms of OMA, squelching the transmitter by setting the OMA to a low level is
recommended.
In module operation, where Tx Squelch is implemented, the default case has Tx Squelch active. Tx Squelch can
be deactivated using Tx Squelch Disable through the TWI serial interface.
Control Interface
Low Speed Control Pins
In addition to the 2-wire serial interface the transceiver has the following low speed signals for control and status:
LPMode/TxDis, ResetL, ModSel, IntL/RxLOS and ModPrsL. See the QSFP112 MSA Specification for detailed
descriptions of each signal.
Low Speed Electrical Specifications
Low speed signaling other than SCL and SDA is based on Low Voltage TTL (LVTTL) operating at Vcc.
Low Speed Control and Sense Signals
2-Wire Management Interface
A management interface, as already commonly used in other form factors like QSFP, SFP, is specified in order to
enable flexible use of the module by the user. This QSFP112 specification is based on CMIS but with
modifications to support a 4 channel module. Byte 00h or Byte 128h on Page 00h is used to indicate the use of
CMIS.
The QSFP112 Module supports alarm, control and monitor functions via a two-wire interface bus. Upon module
initialization, these functions are available. QSFP112 two-wire electrical interface consists of 2 pins of SCL (2-wire
serial interface clock) and SDA (2-wire serial interface data). The low speed signaling is based on Low Voltage
CMOS (LVCMOS) operating at Vcc. Hosts shall use a pull-up resistor connected to Vcc_host on the 2-wire
interface SCL (clock) and SDA (Data) signals. The timing requirements on the two-wire interface are listed in
Table below and Figure below.
Management Interface Timing
Note:
1. When the host has determined that module is QSFP112, the management registers can be read to determine
alternate supported ModSelL set up and hold times.
Soft Control and Status Functions
Control and Status Timing Requirements
Notes:
1. Power on is defined as the instant when supply voltages reach and remain at or above the minimum level
specified in the Table of Absolute Maximum Ratings.
2. Measured from the rising edge of SDA in the stop bit of the read transaction.
3. Rx LOS condition is defined at the optical input by the relevant standard.
4. Measured from the rising edge of SDA in the stop bit of the write transaction.
Squelch and Disable Assert/De-assert and Enable/Disable Timing
I/O Timing for Squelch & Disable
Notes:
1.Measured from LOW to HIGH SDA signal transition of the STOP condition of the write transaction. 2.CMIS 4.0
and beyond the listed values are superseded by the advertised DataPathTxTurnOff_MaxDuration and
DataPathTxTurnOn_MaxDuration times in P01h.168.
3.Listed values place a limit on the DataPathTxTurnOff_MaxDuration and DataPathTxTurnOn_MaxDuration times
(P01h.168) that can be advertised by such modules (for CMIS 4.0 and beyond).
Power
The power supply has three designated pins, VccTx, Vcc1, VccRx, in the connector. Vcc1 is used to supplement
VccTx, and VccRx at the discretion of the module vendor. Power is applied concurrently to these pins.
A host board together with the QSFP112 module(s) forms an integrated power system. The host supplies stable
power to the module. The module limits electrical noise coupled back into the host system and limits inrush
charge/current during hot plug insertion.
All power supply requirements in the Table of Absolute Maximum Ratings. shall be met at the maximum power
supply current. No power sequencing of the power supply is required of the host system since the module
sequences the contacts in the order of ground, supply and signals during insertion.
QSFP112 modules are categorized into several power classes as listed in Table below. The power class of
LAQ70-DR4 is class 8.
Table below lists the required timing performance for software control and status functions.
Host Board Power Supply Filtering
The host board should use the power supply filtering equivalent to that shown in Figure below.
Module Power Supply Specification
In order to avoid exceeding the host system power capacity, upon hot-plug, power cycle or reset, all QSFP112
modules shall power up in Low Power Mode if LPMode is asserted. If LPMode is not asserted, the module will
proceed to High Power Mode without host intervention. Figure below shows waveforms for maximum
instantaneous, sustained and steady state currents for Low Power and High Power modes. Specification values
for maximum instantaneous, sustained and steady state currents at each power class are given in the Table of
Absolute Maximum Ratings.
References
1. IEEE - "Std 802.3-2022 Section 8"
2. IEEE - "Std 802.3ck-2022"
3. QSFPDD MSA - "QSFP-DD Management Interface Specification Rev 5.1"
4. QSFP112 MSA - "QUAD SMALL FORM FACTOR PLUGGABLE MODULE 112 Specification Rev.2.1.1"
5. QSFPDD MSA - " QSFP-DD Hardware Specification for QSFP DOUBLE DENSITY 8X PLUGGABLE
TRANSCEIVE Rev. 6.01"
6. SNIA - "SFF-8636 Rev 2.5"
Product Sample Disclaimer
Functional sample: The purpose of this sample is to check and confirm the product feasibility. This sample may be
an R&D prototype or may be a modified current product. This sample may not be manufactured in qualified
production lines nor using qualified components. Link-all guarantees the requested performance of BOL
(Beginning Of Life). Any qualification will not be applied.
Working sample: The purpose of this sample to evaluate, confirm and finalize product specifications. Link-all
guarantees the performance of BOL (Beginning Of Life). Not all qualifications may be completed. This sample
may not be manufactured in qualified production lines nor be using qualified components. Until Link-all releases
the products for general availability, Link-all reserves the right to change prices, features, functions, specifications,
capabilities and release schedule.
Note:
1.There is no differentiation of the part number depending on the product status. Product status should be
confirmed when purchase orders are placed.
Safety Specification Design
Do not look into fiber end faces without eye protection using an optical meter (such as magnifier and microscope)
within 100 mm, unless you ensure that the laser output is disabled. When operating an optical meter, observe the
operation requirements.
CAUTION-Use of controls or adjustments or performance of procedures other than those specified herein may
result in hazardous radiation exposure.
Notice
The information provided on these pages contains the product target specifications which are subject to
change without notice.
Check with Link-all Sales Office for product updates, changes in specifications, sample availability and
production release dates.
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