400G QSFP-DD DR4+ Optical Transceiver
Product Description
Link-all's LAQD-DR4+ is a 4 x 100G QSFP-DD FR1 optical transceiver that provides 4 parallel 100GE links over 4 single mode fiber (SMF) pairs via its MPO-12 connector. Each fiber pair link is compliant to 100GBASE-FR1 and thus can support a 400GE to 4 x 100GE breakout over 2 km. It combines 8x 26.5625 GBd PAM4 electrical lanes into 4 x 53.125 GBd PAM4 optical lanes. Superior performance and reliability is achieved through Link-all's advanced transmitter and receiver design using cooled EA-DFB-LDs each at a CWDM 1.3 µm wavelength and 4 x
PIN PDs. Product Features.
Breakout Mode
4 x 100GBASE-FR1 compliant 53.125GBd PAM4
4 x 100GAUI-2 compliant 2x 26.5625 GBd PAM4
Aggregation Mode
400 Gb/s Ethernet Protocol 4 x 53.125GBd PAM4
400GAUI-8 Compliant 8x 26.5625 GBd PAM4
QSFP-DD MSA compliant
Up to 2 km transmission on single mode fiber with FEC
MPO-12 connector with 8° angled end-face
Power consumption <8 W
Operating case temperature: 0 to +70°C
CMIS 4.0 management interface
RoHS compliant
Applications
1. Data Center 400GE 2 km SMF links
2. 400GE to 4 x 100GE breakout over 2 km
3. Switch/Router interconnections
Ordering Information
| Part number |
Description |
| LAQD-DR4+ |
400GE QSFP-DD DR4+ Transceiver DDM 2KM(FEC), MTP/MPO Receptacle, Commercial Temperature |
Notes:
If you need more customized services, please contact us.
Function Descriptions
Link-all's LAQD-DR4+ is a fully integrated, 425 Gb/s optical transceiver for links up to 2 km by means PSM to the transmit and receive ports of the MPO-12 connector. In Breakout Mode, LAQD-DR4+ is complied with the optical interface specification IEEE Std 802.3-2022 Section 8 100GBASE-FR1 per lane. 100GBASE-FR1 specifies the
use of PAM4 at 53.125 Gbaud operating at the channel with wavelength on the range of 1304.5-1317.5 nm from cooled EA-DFB-LDs and LAQD-DR4+ has four of the lanes with 100GBASE-FR1. The bit rate per lane is 106.25 Gb/s. The received optical lanes are specified by 100GBASE-FR1 per lane and paralleled from the receive MPO- 12 connector ports to 4 PIN-PDs with transimpedance amplifiers (TIAs) to recover the PAM4 for interfacing with the electrical interface.
The electrical interface is in compliance with 100GAUI-2 specified in IEEE Std 802.3-2022 Section 8. 100GAUI-2 specifies the use of two differential electrical lanes operating at 26.5625 GBd PAM4 per lane. The bit rate per lane is 53.125 Gb/s. LAQD-DR4+ has four sets of the two lanes specified by 100GAUI-2. By means of a 2:1 mux/demux in DSP, 100GBASE-FR1 optical interface is connected to 100GAUI-2 electrical interface.
In addition, by selecting Aggregation Mode, LAQD-DR4+ transmits aggregated data rate of 425Gbps defined by IEEE Std 802.3-2022 Section 9. The aggregated data specifies the use of PAM4 at 53.125 Gbaud operating at four parallel channels. The bit rate per lane is 106.25 Gb/s, which produces an aggregate data rate of 425 Gb/s by means PSM to the transmit ports of the MPO-12 connector. The received optical lanes are paralleled from the
receive MPO-12 connector ports to recover the PAM4 for interfacing with the electrical interface. 400GAUI-8 specifies the use of eight differential electrical lanes operating at 26.5625 GBd PAM4 per lane, and it is defined by IEEE Std 802.3-2022 Section 8. The bit rate per lane is 53.125 Gb/s, resulting in an aggregate data rate of 425 Gb/s that matches the optical line interface. An internal gear box in DSP converts between the eight lanes of the host interface and the four lanes of the line interface.
The bit error ratio (BER) of the optical interface is required by 100GBASE-R (Breakout Mode) and 400GBASE-R (Aggregation Mode) to be less than 2.4 x 10-4. The host side shall have Forward Error Correction (FEC) capability based on RS(544,514) requirements defined by IEEE Std 802.3-2022 Section 8 to meet the frame loss ratio requirements of 4 x 100GE and 400GE.
The form factor of LAQD-DR4+ is QSFP56-DD Type 2A and is compliant with the hardware and Common Management Interface Specifications (MIS) of the QSFP-DD multi-source agreement (MSA). QSFP-DD modules can support up to eight electrical lanes on the host interface, which is double the number of lanes supported by QSFP28 or QSFP+ modules. The unique feature of QSFP-DD ports is that they are mechanically and electrically compatible with QSFP28 and QSFP+. Hence, the same port can be used to support multiple generations of modules and data rates if the networking hardware is designed for such operation.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings will cause permanent damage and/or adversely affect device reliability.
Operating Environments
Electrical and optical characteristics below are defined under this operating environment, unless otherwise specified.
Optical Characteristics(per lane)
Notes:
1. Average launch power, each lane (min) is informative and not the principal indicator of signal strength. A transmitter with launch power below this value cannot be compliant; however, a value above this does not ensure compliance.
2. Transmitter reflectance is defined looking into the transmitter.
3. Average receive power, each lane (min) is informative and not the principal indicator of signal strength. A received power below this value cannot be compliant; however, a value above this does not ensure compliance.
4. For when Pre-FEC BER is 2.4 x 10(-4).
5. Measured with conformance test signal at TP3 (see IEEE Std 802.3-2022 clause 140.7.10) for the BER specified in IEEE Std 802.3-2022 clause 140.1.1. 6. These test conditions are for measuring stressed receiver sensitivity. They are not characteristics of the receiver.
Figure 2 Transmitter OMAouter versus TDECQ and Receiver sensitivity (OMAouter) versus TECQ
Electrical Characteristics
Notes:
1. Electrical module output is squelched for loss of optical input signal.
2. IEEE Std 802.3-2022 Section 6
High Speed Data Interface
Rx(n)(p/n)
Rx(n)(p/n) are QSFP-DD module receiver data outputs. Rx(n)(p/n) are AC-coupled 100 Ohm differential lines that should be terminated with 100 Ohm differentially at the Host ASIC. The QSFP-DD module host interface is internally AC coupled, so AC-coupling is not required on the host PCB. Output squelch for loss of optical input signal (RX Squelch) is required and functions as follows. In the event of the Rx input signal on any optical port becoming equal to or less than the level required to assert LOS, the receiver output(s) associated with that Rx port is squelched. A single Rx optical port can be associated with more than one Rx output. In the squelched state, output impedance levels are maintained, while the differential voltage amplitude is less than 50 mVpp.
Tx(n)(p/n)
Tx(n)(p/n) are QSFP-DD module transmitter data inputs. They are AC-coupled 100 Ohm differential lines with 100 Ohm differential terminations inside the QSFP-DD optical module. The AC coupling is implemented inside the QSFP-DD optical module and not required on the Host board. Output squelch for loss of electrical signal (Tx Squelch) is an optional function. Where implemented, it functions as follows. In the event of the differential, peak-to-peak electrical signal amplitude on any electrical input channel becoming less than 150 mVpp, then the transmitter optical output associated with that electrical input channel is squelched and the associated TxLOS flag set. If multiple electrical input channels are associated with the same optical output channel, the loss of any of the incoming electrical input channels causes the optical output channel to be squelched. For applications, e.g. Ethernet, where the transmitter off condition is defined in terms of average power, squelching by disabling the transmitter is recommended and for applications, e.g. InfiniBand, where the transmitter off condition is defined in terms of OMA, squelching the transmitter by setting the OMA to a low level is recommended.
Control Interface
Low Speed Control Pins
In addition to the 2-wire serial interface the transceiver has the following low speed signals for control and status: LPMode, ResetL, ModSel, IntL and ModPrsL. See the QSFP-DD MSA Hardware Specification for detailed descriptions of each signal.
Low Speed Electrical Specifications
Low speed signaling other than SCL and SDA is based on Low Voltage TTL (LVTTL) operating at Vcc.
Low Speed Control and Sense Signals
2-Wire Management Interface
A management interface, as already commonly used in other form factors like QSFP, SFP, and CDFP, is specified in order to enable flexible use of the module by the user. This QSFP-DD specification is based on SFF-8636 but with modifications to support an 8-channel module, and as such is not directly backwards compatible with SFF-8636. Byte 00 on the Lower Page or Address 128 Page 00 is used to indicate the use of the QSFP-DD memory map rather than the QSFP memory map.
The QSFP-DD Module supports alarm, control and monitor functions via a two-wire interface bus. Upon module initialization, these functions are available. QSFP-DD two-wire electrical interface consists of 2 pins of SCL (2-wire serial interface clock) and SDA (2-wire serial interface data). The low speed signaling is based on Low Voltage CMOS (LVCMOS) operating at Vcc. Hosts shall use a pull-up resistor connected to Vcc_host on the 2-wire interface SCL (clock) and SDA (Data) signals. The timing requirements on the two- wire interface are listed in Table and Figure below.
Management Interface Timing
Notes:
When the host has determined that module is QSFP-DD, the management registers can be read to
determine alternate supported ModSelL set up and hold times.
Soft Control and Status Functions
Table below lists the required timing performance for software control and status functions.
Control and Status Timing Requirements
Notes:
1. Power on is defined as the instant when supply voltages reach and remain at or above the minimum level specified in Table "Operating Environment" .
2. Measured from the rising edge of SDA in the stop bit of the read transaction.
3. Measured from the rising edge of SDA in the stop bit of the write transaction.
4. Rx LOS condition is defined at the optical input by the relevant standard.
Squelch and Disable Assert/De-assert and Enable/Disable Timing
I/O Timing for Squelch & Disable
Notes:
1. Measured from LOW to HIGH SDA signal transition of the STOP condition of the write transaction.
2. CMIS 4.0 and beyond the listed values are superseded by the advertised DataPathTxTurnOff_MaxDuration and DataPathTxTurnOn_MaxDuration times in P01h.168.
3. Listed values place a limit on the DataPathTxTurnOff_MaxDuration and DataPathTxTurnOn_MaxDuration times (P01h.168) that can be advertised by such modules (for CMIS 4.0 and beyond)
Power
The power supply has six designated pins, VccTx, VccTx1, Vcc1, Vcc2, VccRx, VccRx1 in the connector. Vcc1 and Vcc2 are used to supplement VccTx, VccTx1, VccRx or VccRx1 at the discretion of the module vendor. Power is applied concurrently to these pins. A host board together with the QSFP-DD module(s) forms an integrated power system. The host supplies stable power to the module. The module limits electrical noise coupled back into the host system and limits inrush charge/current during hot plug insertion. All power supply requirements in Table " Operating Environment " shall be met at the maximum power supply current. No power sequencing of the power supply is required of the host system since the module sequences the contacts in the order of ground, supply and signals during insertion. QSFP56-DD modules are categorized into several power classes as listed in Table below. The power class of LAQD-DR4+ is class 4.
Host Board Power Supply Filtering
The host board should use the power supply filtering equivalent to that shown in Figure 5.
Module Power Supply Specification
In order to avoid exceeding the host system power capacity, upon hot-plug, power cycle or reset, all QSFP- DD modules shall power up in Low Power Mode if LPMode is asserted. If LPMode is not asserted, the module will proceed to High Power Mode without host intervention. Figure 6 shows waveforms for maximum instantaneous, sustained and steady state currents for Low Power and High Power modes. Specification
values for maximum instantaneous, sustained and steady state currents at each power class are given in Table "Operating Environment ".
Pin Description
Regulatory Compliance
References
1. IEEE - "Std 802.3-2022 Section8"
2. IEEE - "Std 802.3-2022 Section9"
3. IEEE - "Std 802.3-2022 Section6"
4. QSFPDD MSA - " QSFP-DD Hardware Specification for QSFP DOUBLE DENSITY 8X PLUGGABLE TRANSCEIVE Rev.
5.1" 5. QSFPDD MSA - " QSFP-DD Management Interface Specification Rev 4.0"
6. SNIA - "SFF-8636 Rev 2.5"
Mechanical Dimensions
Safety Specification Design
Do not look into fiber end faces without eye protection using an optical meter (such as magnifier and microscope) within 100 mm, unless you ensure that the laser output is disabled. When operating an optical meter, observe the operation requirements. CAUTION-Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.
Notice
The information provided on these pages contains the product target specifications which are subject to change without notice. Check with Link-all Sales Office for product updates, changes in specifications, sample availability and production release dates.
Product Sample Disclaimer
Functional sample: The purpose of this sample is to check and confirm the product feasibility. This sample may be an R&D prototype or may be a modified current product. This sample may not be manufactured in qualified production lines nor using qualified components. Link-all guarantees the requested performance of BOL (Beginning Of Life). Any qualification will not be applied.
Working sample: The purpose of this sample to evaluate, confirm and finalize the product specifications. Link-all guarantees the performance of BOL (Beginning Of Life). Not all qualifications may be completed. This sample may not be manufactured in qualified production lines nor be using qualified components. Until Link-all releases the products for general availability, Link-all reserves the right to change prices, features, functions, specifications, capabilities and release schedule. Note: There is no differentiation of the part number depending on the product status. Product status should be confirmed when purchase orders are placed.
Absolute Maximum Ratings
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