1. Function Description
The module is intended to be used on system integrators host board to support transmission over DWDM links in Metro networks. As shown in Figure 1-1, it is comprised of high-data lanes, a single reference clock from hosts, a single 3.3 V power supply, an MDIO interface, and dedicated alarm and control pins. The OM8769XX200 module uses a 104 pin CFP2 MSA connector for all electrical interfaces with the host board, whereas the optical interfaces on the line side are provided through the optical receptacles on the CFP2. The module can be portioned into three functional parts: Tx path, Rx path and Control & Power block. All control interface pins are routed to the MCU and oDSP. MCU is also used for other fast controls needed inside the module such as modulator bias adjustment, firmware management, overall control coordination and status reporting.
Figure 1-1 OM8769XX200 module block diagram
2. Absolute Maximum Ratings
It has to be noted that the operation in excess of any individual absolute maximum ratings might cause permanent damage to this module.
Table 2-1 Absolute Maximum Ratings
Parameter Symbol Min. Typ. Max. Unit Note
Power supply voltage Vcc -0.3 3.3 3.6 V Storage temperature Ts -40 85 °C Relative humidity RH 15 85 % Non-condensing Receiver damage threshold PRdmg 10 dBm
HiSilicon Optoelectronics Confidential January 2023 Rev Draft 2--
3. Operating Environments
Table 3-1 Operating Environments
Parameter Symbol Min. Typ. Max. Unit Note
Case temperature Top 0 70 °C Supply voltage Vcc 3.2 3.3 3.4 V Supply current Icc 11.25 A Steady state Power supply noise Vrip 1 3 % DC-1 MHz 1-10 MHz Module power consumption Pcc 33 36 W Framer enable Module power consumption Pcc 30 33 W Framer bypass
Maximum total power value is specified across the full temperature (0°C-70°C) and voltage range (3.2 V-3.4 V).
4. Electrical Characteristics
4.1 Host Electrical Connector & Pin Assignments
Table 4-1 TOP pin function definition
Pin Numbe Name of Pin Structure (Input/Output) Logic Description 104 GND GND Ground Ground
103 TX4n I CML Transmitter lane 4 102 TX4p I CML
101 GND GND Ground Ground
100 TX3n I CML Transmitter lane 3 99 TX3p I CML
98 GND GND Ground Ground
97 TX2n I CML Transmitter lane 2
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