100/200G DCO CFP2 Transceiver 50GHz ITU-T Grid C Band-LC 96CH

• Customization: Available
• Type: Single Mode or Multimode
• Connection Structure: LC
• Model NO.: LACF2-DCO-200G
• Material Shape: Flat Wire
• Allowed Lateral Pressure: 100(N/100mm)
• Allowed Tensile Strength: <100N
• Core: Multicore
• Certification: RoHS, CE, ISO9001, FCC
• Brand: Link-All or OEM
• Sheath Material: Blister Box
• Condition: New
• Transport Package: Blister Pack
• Trademark: Link-all
• Origin: China
• HS Code: 8517706000
• Production Capacity: 100, 000 Per Year

Product Description

LACF2-DCO 200G
100/200G DCO CFP2 50GHz ITU-T Grid C Band-LC
200G PM-16QAM/100G PM-DQPSK/100G PM-QPSK Modulation
PRODUCT FEATURES  

1. Transmission reach beyond 1300 km/3000 km over SMF for 200G/100G
2. Hot-pluggable
3. Support PM-16QAM(200G) and PM-DQPSK/PM-QPSK(100G) modulation
4. Supports SD-FEC
5. Supports 100G/200G Flex-rate
6. Supports OTU4/OTUC2/2 x 100GE/100GE signaling
7. Compliant with CEI-28G-MR specifications
8. Compliant with OTL4.4/OTLC2/CAUI-4 signaling
9. Compliant with CFP2 MSA Hardware Specification Rev. 1.0
10. Compliant with OIF-CFP2-DCO-01.0
11. Compliant with CFP MSA Management Interface Specification Version 2.6 (R06a)
12. Line & client PRBS generator and checker
13. Line loopback, host terminal/facility loopback
14. Power consumption: 26 W (200G)/21 W (100G)

Host Interface Configuration

The module supports host signal types: OTUC2/OTU4/100GE/2 x 100GE. The host electrical interfaces are compliant with CEI-28G-MR. The host rate is dependent on the framing type and the supported host rates are shown in the following table. Clock source is need for synchronization, and module REFCLK input clock = Host Baud Rate/160.

Host Frame	Signaling	Data Rate (Gbps)	REFCLK Clock
200G OTUC2	OTLC2 NRZ	28.076	175.476 MHz, ±20 ppm
100G OTU4	OTL4.4 NRZ	27.952	174.703 MHz, ±20 ppm
100GE	CAUI-4 NRZ	25.78125	NA

Line Framing Format

The line framing format is Link-all proprietary and it is required that both ends of the optical connection use Link-all technologies, in which there is proprietary SD-FEC in conjunction with 200G PM-16QAM/100G PM-DQPSK/100G PM-QPSK modulation.
The actual line rate depends on the configured FEC mode and the host data format.

Line Data Rate	Min Grid Spacing (GHz)	Baud Rate (Gbaud)	Modulation Format	FEC OH	Rx OSNR(dB) EOL @Pre-FEC BER
200G	50	39.7	PM-16QAM	25%	17
100G	50	33.6	PM-QPSK /PM-DQPSK	25%	11.5/13

Configuration Overview
The table below summarizes the possible combinations of host type and line side (modulation) that can be configured through the MDIO interface. Refer to the LACF2-DCO-200G software interface specification for register details needed to configure the CFP2 for the desired application.

Host Format	Host Signaling	Line Side Configuration	FEC	Line Format
OTUC2	OTLC2	PM-16QAM	SD-FEC	Link-all proprietary
OTU4	OTL4.4	PM-DQPSK	SD-FEC	Link-all proprietary
OTU4	OTL4.4	PM-QPSK	SD-FEC	Link-all proprietary
2 x OTU4	OTL4.4	PM-16QAM	SD-FEC	Link-all proprietary
2 x 100GE	2 x CAUI-4	PM-16QAM	SD-FEC	Link-all proprietary
100GE	CAUI-4	PM-QPSK	SD-FEC	Link-all proprietary

Environmental Specifications
The table below defines the environmental specifications of the LACF2-DCO-200G module.

Parameter	Min	Max	Unit	Condition
Environmental storage Temperature	-40	85	°C
Environmental storage (relative) humidity	-	85	%
Environmental operating (relative) humidity	-	85	%
Operating temperature	0	75	°C	This temperature is monitored through an internal thermal sensor (MDIO register B02F). The temperature reading represents the module case temperature at the specified location.
Short term operating at high temperature	-	80	°C	The module operates up to a maximum temperature for short term (96 hours continuously, less than 15 days per year). This temperature is monitored through an internal thermal sensor (MDIO register B02F). The temperature reading represents the module case temperature at the specified location.

Absolute Maximum Ratings
Operating or handling the module out of any specified absolute maximum rating is subject to permanent damage of the module.
 

Parameter	Min	Max	Unit	Condition
Operating case temperature	-10	85	°C	This temperature is monitored through an internal thermal sensor (MDIO register). The temperature reading represents the module case temperature at the specified location.
Power supply	-0.3	3.7	V
Rx input power	-	14	dBm	Same modulation format; same wavelength as Rx local oscillator; continuous or peak power

Electrical Characteristics
A single +3.3 V power supply shall be provided by the host card through the 104-pin connector and internal DC/DC power converters are used to regulate the power for different components inside the module. The +3.3 V power supply provided by the host shall adhere to the CFP2 MSA Hardware Specification version1.0 available at . The electrical ground is isolated from the module chassis ground.
The power supply requirements are specified in Table 8-1 below. Those power classes for which the maximum current per pin exceeds 1125 mA will require agreement from the electrical connector supplier.

Parameter	Symbol	Min	Typ	Max	Unit	Note
3.3 V DC supply voltage	P3V3	3.2	3.3	3.4	V	Measured at the electrical connector
3.3 V DC supply current	P3V3_Icc	-		9	A	The maximum current/pin shall not exceed 1.125 A
Power supply noise	P3V3_noise	-		2	%p-p	DC-500 MHz
Power supply ripple	P3V3_ripple	-		1	%p-p	DC-20 MHz
lnrush current	P3V3_Iir			500	mA/μs
Turn-off current	P3V3_Ito	-500			mA/μs
Power consumption	Pwlp	-		2	W	Low power mode
Power consumption	Pwc4	-		26^*1, *2	W	200G PM-16QAM
		-		21^*1, *2	W	100G PM-DQPSK/QPSK

Notes:

Power consumption depends on the actual application condition. For 200G PM-16QAM typical application, optical links should have enough OSNR margin with pre-BER better than 1.5e-2 and power consumption is less than 26 W (200G with framer enabled)/21 W (100G with framer enabled)
With framer disabled, the power consumption will be reduced to 25 W for 200G or 20 W for 100G.
The LACF2-DCO-200G module supports alarm, control, and monitoring functions over an MDIO bus. This interface consists of eight pins listed in the table below.

Signal	I/O	Logic	Description
MDC	I	1.2 V LVCMOS	Management data clock, max. 4 MHz
MDIO	I/O	1.2 V LVCMOS	Management data input output, max. 4 Mbps
PRTADR[2:0]	I	1.2 V LVCMOS	Physical port address
GLB_ALRMN	O	3.3 V LVCMOS	Global alarm, active low, indicating FAWS condition

There are six control pins as listed in the following table to support real-time control via hardware pins.

Signal	I/O	Logic	Description
MOD_RSTN	I	3.3 V LVCMOS	Module reset, active L, internal PD
TX_DIS	I	3.3 V LVCMOS	Transmitter disable, active H, internal PU
MOD_LOPWR	I	3.3 V LVCMOS	Module low power, active H, internal PU
PRG_CNTL[2:1]	I	3.3 V LVCMOS	Programmable control [2:1], internal PU

The PRG_CNTRL [2:1] signals have MSA defined default meanings that are listed in the CFP MSA implementation agreement. The lower two bits (hardware interlock) define the power class of the module and must be kept static during initialization. When MOD_LOPWR is active, the maximum power consumption is < 2 W and the host can still communicate with the module via the MDIO interface.
The MOD_RSTN signal is run to a reset chip to generate a reset to the internal MCU and oDSP ASIC (RST_N). There are five alarm pins from the module back to the host.

Signal	I/O	Logic	Description
RX_LOS	O	3.3 V LVCMOS	Receiver loss of signal, active H
MOD_ABS	O	3.3 V LVCMOS	Module absent, active H, internal PD
PRG_ALRM[2:1]	O	3.3 V LVCMOS	Programmable alarm [2:1]

All signals but MOD_ABS interface to the DSP ASIC. The PRG_ALRM [2:1] signals have MSA defined default meanings that are listed in the CFP2 implementation agreement.
The transmitter and receiver comply with the CEI-28G-MR electrical specification. The data lines are AC-coupled and terminated in the module according to the following figure from the CFP2 MSA. The termination also applies to the reference clock, TX monitor clock, and RX monitor clock.

Parameter	Symbol	Min	Typ	Max	Unit	Notes
Signaling rate per lane	TBaud	25.78		28.3	Gbps	CEI-28G-MR
Differential voltage pk-pk	TVdiff	800		1200	mVpp
Differential output Impedance	TRD	80	100	120
Common mode noise (RMS)	Vrms	/	/	/	mV	AC-coupled
Transition time	Trise/Tfall		TBD		ps	20% to 80%
Common return loss	TSCC22			-6	dB	< 10 GHz
				-4	dB	10 GHz~Baud Rate
Total jitter				0.28	UIpp

 

Parameter	Symbol	Min	Typ	Max	Unit	Notes
Signaling rate per lane	RBaud	25.78		28.3	Gbps	CEI-28G-MR
Differential voltage pk-pk	RVdiff		TBD		mVppd	Compliant with CEI-28G-MR
Common mode noise (RMS)	Vrms		TBD		mV	AC coupled
Transition time	Trise/Tfall		TBD		ps	20% to 80%
Differential input impedance	RRD	80	100	120
Common return loss	RSCC11			-6	dB	< 10 GHz
				-4	dB	10GHz~Baud Rate
Sinusoidal jitter, maximum	R_SJ-max			5	UIpp
Sinusoidal jitter, high frequency	R_SJ-hi			0.05	UIpp
Offset of frequency				20/100	ppm	OTN/ETH

Optical Characteristics

All specifications given in this document are End-of-Life numbers and are valid over the operating temperature. The two tables below contain specifications of the general transmitter and the general receiver. Specifications are common across the Link-all Metro product family.

 

Parameter	Min	Typ	Max	Unit	Condition/Comment
Transmitter frequency range	191.3		196.05	THz	ITU-T 50 GHz grid
Transmitter laser frequency stability	-1.5		1.5	GHz
Transmitter output power range	-10		1	dBm	Default 0.5 dBm
Output power stability (standard range)	-0.3		0.3	dB
Output power accuracy and stability (standard range)	-1		1	dB
Transmitter laser disable time	-		10	ms
Transmitter wavelength switching time	-		60	s
Transmitter turn-up time from cold start		60	120	s
Transmitter OSNR	35			dB/0.1 nm	OSNR at transmitter output (in-band)
Transmitter signal-to-max ASE	TBD			dB/0.1 nm	Signal to the maximum out-of-band ASE level
Transmitter optical return loss	24			dB
Transmitter output power with TX disabled			-35	dBm	E.g., max. output power when changing laser frequency.
Transmitter polarization dependent power			1	dB	Power deference between X and Y polarization

Parameter	Min	Typ	Max	Unit	Condition/Comment
Receiver frequency range	191.3		196.05	THz
Optimum input power range	-14		0	dBm	Signal power of the selected channel. The input power range gets optimum OSNR performance
Extended input power range	-18		0	dBm	@0.5 dB OSNR penalty
OSNR tolerance (BOL)		16.2	16.7	dB/0.1 nm	200G PM-16QAM
		10.6	11	dB/0.1 nm	100G PM-QPSK
		12.3	12.8	dB/0.1 nm	100G PM-DQPSK
CD tolerance	-10,000		40,000	ps/nm	200G PM-16QAM with less than 0.5 dB OSNR penalty
	-10,000		100,000	ps/nm	100G PM-DQPSK/QPSK with less than 0.5 dB OSNR penalty
PMD tolerance	25			ps	200G PM-16QAM with less than 1.0 dB OSNR penalty
PMD tolerance	30			ps	100G PM-DQPSK/QPSK with less than 1.0 dB OSNR penalty
PDL tolerance	6			dB	Single optical stress. < 1 dB OSNR penalty @2 dB PDL < 2 dB OSNR penalty @4 dB PDL < 4 dB OSNR penalty @6 dB PDL
	3			dB	Multiple optical stress, such as SOP, DGD, etc.
Optical input power transient tolerance	6			dB
Tolerance to change in SOP	628			rad/ms	200G PM-16QAM Single optical stress. < 0.5 dB OSNR penalty @314 rad/ms < 1 dB OSNR penalty @628 rad/ms
	314			rad/ms	200G PM-16QAM Multiple optical stress,such as PDL, DGD, etc.
	1000		-	rad/ms	100G PM-DQPSK/QPSK Single optical stress. < 0.5 dB OSNR penalty@628 rad/ms < 1 dB OSNR penalty@1000 rad/ms
	628		-	rad/ms	100G PM-DQPSK/QPSK Multiple optical stress, such as PDL, DGD, etc.
Dispersion reading accuracy	-150		150	ps/nm
DGD reading accuracy	-10		10	ps
Multiple optical stress OSNR penalty			1.5	dB	200G PM-16QAM @25 kHz SOP + 3 dB PDL + 25 ps PMD
			1.5	dB	100G PM-DQPSK/QPSK @50 kHz SOP + 3 dB PDL + 25 ps PMD
Input power reading accuracy	-1.5		1.5	dB	Within the range of 0 dBm to -18 dBm
Input power reading accuracy	-2.5		2.5	dB	Within the range of -18 dBm to -25 dBm
Optical return loss	27			dB

Mechanical Specifications

The CFP2 module is designed to be inserted into a host board with a railing system that includes a heat sink. The module is 107.5 mm x 41.5 mm x 12.4 mm in size and is mechanically compliant with the requirements detailed the CFP2 HW Baseline Design Rev.1L.
Notes:
Please check whether the cage matches before using the module because of the side has dissipation hole structure. For example, the cage part CN121C-104-0029(H1) (YAMAICHI) has side openings and a side without sharp protrusions.
The module plug connector is a sub-component within the CFP2 module. The PCB inserts into the connector with top and bottom rows of pins (primary and secondary sides of the PCB). The host connector has a physical offset of the pin contacts to ensure that certain signals make and break contacts before others. The ground mates first, the 3.3V and 3.3 V ground mate second, the control and status signals mate third, and the MOD_LOPWR, MOD_ABS and high speed data signals mate last.
The module connector is a 104-pin plug connector. The connector pinout defined by CFP2 MSA and Link-all (including debug and sub-modulation signals using VND_IO_x pins) is as follows. Customers must not connect to any of the VND_IO_x pins unless specifically allowed to do so.

Bottom		Top (4 x 25G)		Top (8 x 25G)
1	GND	104	GND	104	GND
2	(TX_MCLKn) or Vendor_Out0n	103	N.C.	103	TX4n
3	(TX_MCLKp) or Vendor_Out0p	102	N.C.	102	TX4p
4	GND	101	GND	101	GND
5	Vendor_In0n	100	TX3n	100	TX3n
6	Vendor_In0p	99	TX3p	99	TX3p
7	3.3 V_GND	98	GND	98	GND
8	3.3 V_GND	97	TX2n	97	TX2n
9	3.3 V	96	TX2p	96	TX2p
10	3.3 V	95	GND	95	GND
11	3.3 V	94	N.C.	94	TX5n
12	3.3 V	93	N.C.	93	TX5p
13	3.3 V_GND	92	GND	92	GND
14	3.3 V_GND	91	N.C.	91	TX6n
15	VND_IO_A	90	N.C.	90	TX6p
16	VND_IO_B	89	GND	89	GND
17	PRG_CNTL1	88	TX1n	88	TX1n
18	PRG_CNTL2	87	TX1p	87	TX1p
19	PRG_CNTL3	86	GND	86	GND
20	PRG_ALRM1	85	TX0n	85	TX0n
21	PRG_ALRM2	84	TX0p	84	TX0p
22	PRG_ALRM3	83	GND	83	GND
23	GND	82	N.C.	82	TX7n
24	TX_DIS	81	N.C.	81	TX7p
25	RX_LOS	80	GND	80	GND
26	MOD_LOPWR	79	(REFCLKn)	79	(REFCLKn)
27	MOD_ABS	78	(REFCLKp)	78	(REFCLKp)
28	MOD_RSTn	77	GND	77	GND
29	GLB_ALRMn	76	N.C.	76	RX4n
30	GND	75	N.C.	75	RX4p
31	MDC	74	GND	74	GND
32	MDIO	73	RX3n	73	RX3n
33	PRTADR0	72	RX3p	72	RX3p
34	PRTADR1	71	GND	71	GND
35	PRTADR2	70	RX2n	70	RX2n
36	VND_IO_C	69	RX2p	69	RX2p
37	VND_IO_D	68	GND	68	GND
38	VND_IO_E	67	N.C.	67	RX5n
39	3.3 V_GND	66	N.C.	66	RX5p
40	3.3 V_GND	65	GND	65	GND
41	3.3 V	64	N.C.	64	RX6n
42	3.3 V	63	N.C.	63	RX6p
43	3.3 V	62	GND	62	GND
44	3.3 V	61	RX1n	61	RX1n
45	3.3 V_GND	60	RX1p	60	RX1p
46	3.3V_GND	59	GND	59	GND
47	Vendor_In1n	58	RX0n	58	RX0n
48	Vendor_In1p	57	RX0p	57	RX0p
49	GND	56	GND	56	GND
50	(RX_MCLKn) or Vendor_Out1n	55	N.C.	55	RX7n
51	(RX_MCLKp) or Vendor_Out1p	54	N.C.	54	RX7p
52	GND	53	GND	53	GND

 Notes:

1. 100G OTU4/100GE: TX (RX) 0~3 for OTL4.4/CAUI-4 signaling.
2. 200G OTUC2/2 x 100GE: TX (RX) 0~3 for one OTLC/CAUI-4 signaling, TX (RX) 4~7 for another OTLC/CAUI-4 signaling.

The optical port connections on the front of the CFP2 module are shown in Figure 10-1. The CFP2 module will support LC receptacles for standard single-mode fiber. As mention in the OIF-CFP2-DCO-01.0, the position of the optical connector in the Y and Z axes shall be specified by the CFP2-DCO module manufacturer. In addition to the centered duplex LC connector location specified by the CFP MSA, the CFP2-DCO IA also optionally allows the optical port position on the front of the module to be either left or right-justified if needed to enable a certain vendor-specific implementation technology.
Regulatory and Reliability Specifications
Laser Safety
The module is designed to comply with Class 1 laser, according to IEC/EN 60825-1/A2: 2001, or FDA CDRH21 CFR-1040. Don't directly look into the transmitter fiber connector at any time while the module is in operation.

ESD
The module is designed to meet ESD susceptibility up to 500V according to GR-78 (Human Body Model using C = 100 pF, R = 1.5 kOhm) on the high-speed pins and 2000 V for all other pins. Handle only at Static Safe Work Stations.

Electromagnetic Emission
The module is designed to comply with Class B electromagnetic emission according to GR-1089-CORE Sections 3.2.1.1 and 3.2.1.3 .

Electromagnetic Immunity
The module is designed to comply with EMI 8.5V/m per GR.1089-CORE section 3.3.1 .

Flammability
The module is designed to comply with GR-63 section 4.2.3 for fire resistance.

RoHS
The module complies with Directive 2011/65/EC on the restriction on the use of certain hazardous substances in electrical and electronic equipment and with exception 6a, 6c, 7b and 13a permitted by Commission Decision (2010/571/EU).
Reliability
The module is designed to comply with GR-468 for general reliability. Target FIT < 2700 at 55°C operating case temperature

List of Acronyms

BER CD DGD DWDM EOL ESD FEC PDL SD-FEC TBD MDIO MSA NRZ PRBS SMF

Bit error rate Chromatic dispersion Differential group delay Dense wavelength division multiplexing End of life Electro-static discharge Forward error correction Polarization dependent loss Soft decision forward error correction To be defined/To be determined Management data I/O Multi-source agreement Non-return to zero Pseudo random bit sequence Single mode fiber